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description the m32170 and m32174 group are 32-bit single chip risc microcomputers designed for use in general industrial and household equipment. these microcomputers contains a variety of peripheral functions ranging from16-channel a-d converters to 64chan- nel multifunction timers, 10-channel dmas, 6-channel serial i/os, 1-channel real time debugger, 1-channel full-can, and jtag (boundary scan facility). with lower power consumption and low noise characteristics also considered, these microcomputers are ideal for embed- ded equipment applications. features m32r risc cpu core ? uses the m32r family risc cpu core (instruction set common to all microcomputers in the m32r family) ? five-stage pipelined processing ? sixteen 32-bit general-purpose registers ? 16-bit/32-bit instructions implemented ? dsp function instructions (sum-of-products calculation using 56-bit accumulator) ? built-in flash memory ? built-in flash programming boot program ? built-in ram ? pll clock generating circuit ........... built-in 4 pll circuit ? maximum operating frequency of the cpu clock 40mhz(when operating at -40 to +85 o c) 32mhz(when operating at -40 to +125 o c) table 1 32170 group name list by type type name ram size rom size package m32170f6vfp 40k bytes 768k bytes 240qfp m32170f4vfp 32k bytes 512k bytes 240qfp m32170f3vfp 32k bytes 384k bytes 240qfp m32170f6vwg 40k bytes 768k bytes 255fbga m32170f4vwg 32k bytes 512k bytes 255fbga m32170f3vwg 32k bytes 384k bytes 255fbga note: 255fbga is currently under development. table 2 32170 group name list by type type name ram size rom size package m32174f4vfp 40k bytes 512k bytes 240qfp m32174f3vfp 40k bytes 384k bytes 240qfp m32174f4vwg 40k bytes 512k bytes 255fbga m32174f3vwg 40k bytes 384k bytes 255fbga note: 255fbga is currently under development. 64-channel multijunction timers (mjt) multifunction timers are incorporated that support various purposes of use. 16-bit output related timers ....................................... 35ch 16-bit input/output related timers .............................. 10ch 16-bit input related timers ......................................... 11ch 32-bit input related timers .......................................... 8ch ? flexible configuration is possible through interconnection of timers. ? the internal dmac and a-d converter can be started by a timer. real-time debugger ? includes dedicated clock-synchronized serial i/o that can read and write the contents of the internal ram independently of the cpu. ? can look up and update the data table in real time while the program is running. ? can generate a dedicated interrupt based on rtd commu- nication. abundant internal peripheral functions in addition to the timers and real-time debugger, the micro- computer contains the following peripheral functions. ? dmac .............................................................. 10 channels ? two independent a-d converter .............. (10-bit converter 16 channels) 2 ? serial i/o ............................................................ 6 channels ? interrupt controller ........... 31 interrupt sources, 8 priority levels ? wait controller ? full can .............................................................. 1 channel ? jtag (boundary scan function) designed to operate at high temperatures to meet the need for use at high temperatures, the micro- computer is designed to be able to operate in the temperature range of -40 to +125 o c when cpu clock operating frequency = 32 mhz. when cpu clock operating frequency = 40 mhz, the microcomputer can be used in the temperature range of -40 to +85 o c. note: this does not guarantee continuous operation at 125 o c. if you are considering use of the microcom puter at 125 o c, please consult mitsubishi. applications automobile equipment control (e.g., engine, abs, at), indus- trial equipment system control, and high-function oa equip- ment (e.g., ppc) mitsubishi microcomputers single-chip 32-bit cmos microcomputer 32170 group, 32174 group 2001-5-14 rev.1.0
mitsubishi microcomputers 2 2001-5-14 rev.1.0 single-chip 32-bit cmos microcomputer 32170 group, 32174 group figure 1 pin layout diagram of the 240qfp pin assignment(top view) package 240p6y-a m32170f3vfp m32170f4vfp m32170f6vfp 2 4 3 44 43 5 6 7 8 9 35 36 37 38 39 40 22 23 24 25 26 27 2 8 2 9 30 31 32 33 34 11 12 13 1 4 15 16 17 18 19 20 21 41 42 10 1 60 59 51 52 53 54 55 56 45 46 47 48 49 50 57 58 89 90 99 98 97 96 95 94 93 92 91 103 102 101 112 111 110 109 108 107 106 105 104 120 119 118 117 116 115 114 113 63 64 66 67 68 69 70 71 72 73 74 65 84 75 76 77 78 79 80 81 82 83 85 86 87 88 61 62 100 12 4 132 130 12 9 127 121 137 14 6 14 5 144 1 43 142 141 14 0 13 9 13 8 1 55 1 54 15 3 1 52 1 51 1 50 149 148 147 15 6 1 59 1 58 157 133 136 13 5 13 4 123 122 131 12 8 12 6 12 5 1 66 165 16 4 1 63 162 1 61 17 5 17 4 173 172 171 170 169 16 8 1 67 176 179 178 177 1 60 180 195 185 184 183 182 181 186 189 188 187 194 193 192 191 190 196 199 198 197 205 204 203 202 201 200 206 209 208 207 215 214 213 212 211 210 216 239 217 219 218 225 224 223 222 221 220 226 227 229 228 230 235 234 233 232 231 236 237 238 240 p41/blw/ble p157/tin7 p156/tin6 p155/tin5 p154/tin4 p153/tin3 p152/tin2 p151/tin1 p150/tin0 p147/tin15 p146/tin14 p145/tin13 p144/tin12 p143/tin11 p142/tin10 p141/tin9 p140/tin8 vss vcce p137/tin23 p136/tin22 p135/tin21 p134/tin20 p133/tin19 p132/tin18 p131/tin17 p130/tin16 vss vcci p42/bhw/bhe p127/tclk3 p126/tclk2 p125/tclk1 p124/tclk0 p107/to15 p106/to14 p105/to13 p104/to12 vss v cci p103/to11 vss vcci p4 3/rd p44 /cs 0 p45/ cs1 p14 /db12 p37 /a22 p36/ a21 p33/ a18 p31 /a16 p30 /a1 5 p35 /a20 p3 4/ a19 p32 /a17 v cce p27 /a30 p2 5/a2 8 p2 6/a2 9 p2 4/a 27 p07 /db7 p02 /d b2 p01/ db1 p00 /db0 p23 /a 26 p22 /a25 p20 /a23 p10 /d b8 p11 /db 9 v ss p15/ db13 p13 /db11 p12 /db 10 p06 /db 6 p0 4/d b4 p03 /d b3 p47 /a14 p21 /a24 p46/ a13 vcc e v ss p16 /db1 4 p17 /db1 5 p82/txd0 vss vcce p172/tin24 p173/tin25 p174/txd2 p175/rxd2 p176/txd3 p177/rxd3 p160/to21 p161/to22 p162/to23 p163/to24 p164/to25 p165/to26 p166/to27 p167/to28 vss vcci vref0 avcc0 ad0in7 ad0in6 ad0in5 ad0in4 ad0in3 ad0in2 ad0in1 ad0in0 ad0in15 ad0in14 ad0in13 ad0in12 ad0in11 ad0in10 ad0in9 ad0in8 avss0 p181/to30 p182/to31 p183/to32 p184/to33 p180/to29 vss vcce p186/to35 p187/to36 p190/tin26 p185/to34 p194/tin30 p195/tin31 p196/tin32 p197/tin33 p191/tin27 p192/tin28 p193/tin29 re set p84/sclki0/sclko0 p83/rxd0 p85/txd1 p86/rxd1 p 87/s clk i1/s clk o1 v ss v cce vcc i p6 2 vss fp p67 /adt rg p66 /sc lki5 /scl ko5 p6 5/sc lki4 /sc lko 4 p9 4/to 17 p7 4/r tdt xd p7 5/r tdr xd p7 6/r tda ck p77 /rt dc lk p 61 p6 3 p11 4/to 4 p115 /to 5 p11 6/to 6 p117 /to 7 v ss v cce mo d1 p100 /to 8 p101 /to 9 p102 /to10 p110 /to 0 p111 /to 1 p112 /to 2 p113 /to 3 p95 /to 18 p96 /to1 9 p97 /to20 p70 /bcl k/w r p71/w ait p72 / hre q p6 4/sb i mo d0 p9 3/to 16 p73 / hac k vcc i v ss v dd fv cc p201 /rx d4 p202 /tx d5 p203 /rx d5 p200 /tx d4 ad1in5 ad1in4 ad1in3 ad1in2 ad1in1 ad1in0 vref1 ad1in15 ad1in14 ad1in13 ad1in12 av ss1 ad1in6 jtdo jtrst jtck jtms jtdi p212 /to3 9 p213 /to4 0 p21 4/to41 p21 5/to42 p211 /to 38 p210 /to 37 p21 6/to43 p217 /to44 vc nt osc -vcc x out x in osc -vss p221 /cr x p220 /ct x v ss vss p0 5/db 5 ad1in11 ad1in10 ad1in9 ad1in8 ad1in7 p222 p223 (n ote) p22 4/a11 (note) p22 5/a 12 vss avcc1 m32174f3vfp m32174f4vfp note: use caution when using these pins because they nave a debug event function.
mitsubishi microcomputers 3 single-chip 32-bit cmos microcomputer 2001-5-14 rev.1.0 32170 group, 32174 group figure 2 pin layout diagram of the 255fbga package 255fbga abcdefgh jkl mnprt uvwy 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 ad1in12 ad1in13 ad1in14 ad1in15 avss1 p43 /rd p44 /cs0 p45 /cs1 p46 /a13 p47 /a14 p220 /ctx p221 /crx p222 p223 p224 /a11 p225 /a12 vss osc- vss xin xout osc- vcc vss vcnt vss p30 /a15 p31 /a16 p32 /a17 p33 /a18 p34 /a19 p35 /a20 trclk trsync p36 /a21 p37 /a22 p20 /a23 p21 /a24 p23 /a26 p22 /a25 vcce vss p24 /a27 p25 /a28 p26 /a29 p27 /a30 p00 /db0 p01 /db1 p02 /db2 p03 /db3 p04 /db4 p05 /db5 p06 /db6 p07 /db7 vcce vss p10 /db8 p11 /db9 p12 /db10 p13 /db11 p14 /db12 p15 /db13 p16 /db14 p17 /db15 vref0 avcc0 ad0in0 ad0in1 ad0in2 ad0in3 ad0in4 ad0in5 ad0in6 ad0in7 ad0in8 ad0in9 ad0in10 ad0in11 ad0in12 ad0in13 ad0in14 ad0in15 avss0 vcce vss p180 /to29 p181 /to30 p182 /to31 p183 /to32 p184 /to33 p185 /to34 p186 /to35 p187 /to36 p190 /tin26 p191 /tin27 p192 /tin28 p193 /tin29 p194 /tin30 p196 /tin32 p195 /tin31 p197 /tin33 vcci vss p160 /to21 p161 /to22 p162 /to23 p163 /to24 p164 /to25 p165 /to26 p166 /to27 p167 /to28 p172 /tin24 p173 /tin25 p174 /txd2 p175 /rxd2 p176 /txd3 p177 /rxd3 vcce vss p82 /txd0 p87 /sclk1 p84 /sclk0 p85 /txd1 p86 /rxd1 trdata 0 trdata 1 trdata 2 trdata 3 p200 /txd4 p201 /rxd4 p202 /txd5 p203 /rxd5 vcci vss p83 /rxd0 vss p61 p62 fvcc p64 /sbi p65 /sclk4 p66 /sclk5 p63 vcci vss vcce p67 /adtrg p71 /wait p72 /hreq p73 /hack p74/ rtdtxd p75/ rtdrxd p76/ rtdack p77/ rtdclk p93 /to16 p94 /to17 p95 /to18 p96 /to19 p97 /to20 reset mod0 mod1 fp vcce vss p110 /to0 p111 /to1 p112 /to2 p113 /to3 trdata 4 trdata 5 trdata 6 trdata 7 p114 /to4 p115 /to5 p116 /to6 p117 /to7 p100 /to8 p101 /to9 p102 /to10 vdd vcci vss p210 /to37 p211 /to38 p212 /to39 p214 /to41 p215 /to42 p213 /to40 p216 /to43 p217 /to44 jdbi jtck jevent 0 jtrst jevent 1 jtdo jtdi p103 /to11 p104 /to12 p105 /to13 p106 /to14 p107 /to15 p124 /tclk0 p125 /tclk1 p126 /tclk2 p127 /tclk3 vcci vss p130 /tin16 p131 /tin17 p132 /tin18 p133 /tin19 p134 /tin20 p135 /tin21 p136 /tin22 p137 /tin23 vcce vss p140 /tin8 p141 /tin9 p142 /tin10 p143 /tin11 p144 /tin12 p145 /tin13 p146 /tin14 p147 /tin15 p150 /tin0 p151 /tin1 p152 /tin2 p153 /tin3 p154 /tin4 p155 /tin5 p156 /tin6 p157 /tin7 p41 /blw p42 /bhw vcci vss vref1 avcc1 ad1in0 ad1in1 ad1in2 ad1in3 ad1in4 ad1in5 ad1in6 ad1in7 ad1in8 ad1in10 ad1in9 ad1in11 m32170f3vwg m32170f4vwg m32170f6vwg m32174f3vwg m32174f4vwg p70 /bclk jtms n.c n.c pin assignment(top view) note 1: nc pin (w19, y1) shows non-connect. be open state. note 2: use caution when using p224/a11 and p225/a12 because they have a debug event function. note 3: 255fbga is currently under development.
mitsubishi microcomputers 4 2001-5-14 rev.1.0 single-chip 32-bit cmos microcomputer 32170 group, 32174 group figure 3 block diagram pll clock generation circuit internal bus interface address data internal ram ( m32170f6 : 40kb ) ( m32170f4 : 32kb ) ( m32170f3 : 32kb ) internal flash memory ( m32170f6 : 768kb ) ( m32170f4 : 512kb ) ( m32170f3 : 384kb ) m32r cpu core (max 40mhz) multiplier- accumulator (32 16 + 56) dmac (10 channels) multijunction timer (mjt : 64 channels) serial i/o (6 channels) a-d converter (10-bit, 16 channels) 2 wait controller interrupt controller (31 sources, 8 levels) real-time debugger (rtd) external bus interface internal 16-bit bus internal 32-bit bus input/output port(jtag) 157 lines full can (1 channel) 32170/32174 ( m32174f4 : 512kb ) ( m32174f3 : 384kb ) ( m32174f4 : 40kb ) ( m32174f3 : 40kb )
mitsubishi microcomputers 5 single-chip 32-bit cmos microcomputer 2001-5-14 rev.1.0 32170 group, 32174 group table 3 outline performance (1/2) functional block features m32r cpu core m32r family cpu core, internally configured in 32 bits built-in multiplier-accumulator (32 16 + 56) basic bus cycle : 25 ns (internal cpu clock frequency at 40 mhz, internal peripheral clock frequency at 20 mhz) logical address space : 4g bytes, linear general-purpose register : 32-bit register 16, control register: 32-bit register 5 accumulator : 56 bits external data bus 16 bits data bus instruction set 16-bit/32-bit instruction formats 83 instructions/ 9 addressing modes internal flash memory m32170f6 : 768k bytes m32170f4, m32174f4 : 512k bytes m32170f3, m32174f3 : 384k bytes rewrite durability : 100 times internal ram m32170f6, m32174f4, m32174f3 : 40k bytes m32170f4, m32170f3 : 32k bytes dmac 10 channels (dma transfers between internal peripheral i/os, between internal peripheral i/o and internal ram, and between internal rams) channels can be cascaded and can operate in combination with internal peripheral i/o multijunction timer 64 channels of multijunction timers. ? 16-bit output-related timers 35 channels (single-shot, delayed single-shot, pwm, single-shot pwm) ? 16-bit input/output-related timers 10 channels (event count mode, single-shot, pwm, measurement) ? 16-bit input-related timers 11 channels (measurement, event count mode, multiply-by-4 count 3 channels) ? 32-bit input-related timers 8 channels (measurement) flexible timer configuration is possible through interconnection of channels using the event bus. a-d converter 2 independent 10-bit multifunction a-d converters ? input 16 channels 2 ? scan-based conversion can be switched with 4, 8, and 16 ? capable of interrupt conversion during scan ? 8-bit/10-bit readout function available serial i/o 6 channels (the serial i/os can be set for synchronous serial i/o or uart. sio2,3 are uart mode only) real-time debugger (rtd) 1-channels dedicated clock-synchronized serial the entire internal ram can be read or rewritten from the outside without cpu intervention. interrupt controller controls interrupts from internal peripheral i/os (priority can be set to one of 8 levels including interrupt disabled) wait controller controls wait when accessing external extended area (1 to 4 wait cycles inserted + prolonged by external wait signal input) can 16-channels message slots jtag boundary-scan function
mitsubishi microcomputers 6 2001-5-14 rev.1.0 single-chip 32-bit cmos microcomputer 32170 group, 32174 group table 4 outline performance (2/2) function block features clock maximum internal cpu memory clock : 40mhz (access to cpu, internal rom, and internal ram) maximum internal peripheral clock : 20mhz (access to internal peripheral module) maximum external input clock : 10.0mhz, built-in multiply-by-4 pll circuit power supply voltage external i/o : 5v ( 0.5v) or 3.3v ( 0.3v) internal logic : 3.3v ( 0.3v) operating temperature rang -40 to +125 c(internal cpu memory clock 32mhz, internal peripheral clock 16mhz) -40 to +85 c(internal cpu memory clock 40mhz, internal peripheral clock 20mhz) package 0.5mm pitches / 240-pin plastic qfp, 0.8mm pitches / 255-pin fbga (note) note: 255-pin fbga is currently under development.
mitsubishi microcomputers 7 single-chip 32-bit cmos microcomputer 2001-5-14 rev.1.0 32170 group, 32174 group outline of the cpu core the m32170 and m32174 group uses the m32r risc cpu core, and has an instruction set which is common to all micro- computers in the m32r family. instructions are processed in five pipelined stages consisting of instruction fetch, decode, execution, memory access, and write back. thanks to its out-of-order-completion mechanism, the m32r cpu allows for clock cycle efficient, instruction ex- ecution control. the m32r cpu internally has sixteen 32-bit general-purpose registers. the instruction set consists of 83 discrete instruc- tions, which come in either a 16-bit instruction or a 32-bit in- struction format. use of the 16-bit instruction format helps to reduce the code size of a program. also, the availability of 32- bit instructions facilitates programming and increases the per- formance at the same clock speed, as compared to architectures with segmented address spaces. sum-of-products instructions comparable to dsp the m32r cpu contains a multiplier/accumulator that can execute 32 bits 16 bits in one cycle. therefore, it executes a 32 bit 32 bit integer multiplication instruction in three cycles. also, the m32r cpu supports the following four sum-of-prod- ucts instructions (or multiplication instructions) for dsp func- tion use. (1) 16 high-order register bits 16 high-order register bits (2) 16 low-order register bits 16 low-order register bits (3) all 32 register bits 16 high-order register bits (4) all 32 register bits 16 low-order register bits furthermore, the m32r cpu has instructions for rounding the value stored in the accumulator to 16 or 32 bits, and instruc- tions for shifting the accumulator value to adjust digits before storing in a register. because these instructions also can be executed in one cycle, dsp comparable data processing ca- pability can be obtained by using them in combination with high-speed data transfer instructions such as load & address update or store & address update. built-in clock multiplier circuit the clock multiplier circuit multiplies the frequency of the in- put clock signal by 4 to produce the internal operating clock. when the maximum cpu memory clock frequency = 40 mhz, the input clock frequency is 10.0 mhz. three operation modes the m32170 and m32174 group has three operation modes: single-chip mode, external extended mode, and processor mode. these operation modes are changed from one to an- other by setting the mod0 and mod1 pins. address space the m32170 and m32174 groups logical addresses are al- ways handled in 32 bits, providing 4 gbytes of linear address space. the m32170 and m32174 groups address space consists of the following. user space a 2-gbyte area from h0000 0000 to h7fff ffff is the user space. located in this space are the user rom area, external extended area, internal ram area, and sfr (special function register) area (internal peripheral i/o registers). of these, the user rom area and external extended area are located differ- ently depending on mode settings. boot program space a 1-gbyte area from h8000 0000 to hbfff ffff is the boot program area. this space contains the on-board programming program (boot program) used in blank state by the internal flash memory. system space a 1-gbyte area from hc000 0000 to hffff ffff is the system area. this space is reserved for use by development tools such as an in-circuit emulator and debug monitor, and cannot be used by the user.
mitsubishi microcomputers 8 2001-5-14 rev.1.0 single-chip 32-bit cmos microcomputer 32170 group, 32174 group figure 4 pin function diagram of 240qfp xin reset m32170f6vf p , m32170f4 vfp , m32170f 3vfp , m32174f4vf p , m32174f3 vfp clock reset vcci vss 6 16 p20-p27/a23-a30 p30-p37/a15-a22 p46, p47/a13, a14 address bus 20 p00-p07/db0-db7 p10-p17/db8-db15 data bus 16 p72/hreq p73/hack bus control p71/wait interrupt controller p43/rd p44/cs0 p45/cs1 p41/blw/ble p42/bhw/bhe port 22 port 2 port 3 port 4 port 0 port 1 port 7 port 4 xout vcnt osc-vcc osc-vss mod0 mod1 mode p190-p197/tin26-tin33 p172, p173/tin24, tin25 p150-p157/tin0-tin7 p140-p147/tin8-tin15 p130-p137/tin16-tin23 34 port 19 port 17 port 15 port 14 port 13 p124-p127/ tclk0-tclk 3 4 45 p210-p217/to37-to44 p180-p187/to29-to36 p160-p167/to21-to28 p110-p117/to0-to7 p100-p107/to8-to15 p93-p97/to16-to20 port 12 port 21 port 18 port 16 port 11 port 10 port 9 p74/rtdtxd p75/rtdrxd p76/rtdack p77/rtdclk real-time debugger port 7 p70/bclk/wr port 7 p82/txd0 p83/rxd0 p84/sclki0/sclko0 p85/txd1 p86/rxd1 p87/sclki1/sclko1 serial i/o port 8 16 ad1in0-ad1in15 a-d converter p67/adtrg avcc0, avcc1 avss0, avss1 port 6 p61-p63 port 6 avref0, avref1 vdd fvcc fp vcce 7 p174/txd2 p175/rxd2 p176/txd3 p177/rxd3 port 17 3.3v (note 1) 5v 3.3v 5v 3.3v 3.3v 5v note 1: : operates with a 3.3v power supply. : operates with a 3.3v or 5v power supply. 16 ad0in0-ad0in15 2 2 2 p200/txd4 p201/rxd4 p202/txd5 p203/rxd5 port 20 p220/ctx p221/crx can jtms jtck jtrst jtdo jtag jtdi port 22 p222, p223 port 22 p224/a11 (note 2) p225/a12 (note 2) note 2: use caution when using this port because it has a debug event function. p65/sclki4/sclko4 p64/sbi port 6 p66/sclki5/sclko5 port 6 3 multijunction timer
mitsubishi microcomputers 9 single-chip 32-bit cmos microcomputer 2001-5-14 rev.1.0 32170 group, 32174 group figure 5 pin function diagram of 255fbga xin reset m32170f6vwg , m32170f4vwg , m32170f3vwg , m32174f4vwg , m32174f3vwg clock reset vcci vss 6 16 p20-p27/a23-a30 p30-p37/a15-a22 p46, p47/a13, a14 address bus 20 p00-p07/db0-db7 p10-p17/db8-db15 data bus 16 p72/hreq p73/hack bus control p71/wait interrupt controller p43/rd p44/cs0 p45/cs1 p41/blw/ble p42/bhw/bhe port 22 port 2 port 3 port 4 port 0 port 1 port 7 port 4 xout vcnt osc-vcc osc-vss mod0 mod1 mode p190-p197/tin26-tin33 p172, p173/tin24, tin25 p150-p157/tin0-tin7 p140-p147/tin8-tin15 p130-p137/tin16-tin23 34 port 19 port 17 port 15 port 14 port 13 p124-p127/ tclk0-tclk 3 4 multijunction timer 45 p210-p217/to37-to44 p180-p187/to29-to36 p160-p167/to21-to28 p110-p117/to0-to7 p100-p107/to8-to15 p93-p97/to16-to20 port 12 port 21 port 18 port 16 port 11 port 10 port 9 p74/rtdtxd p75/rtdrxd p76/rtdack p77/rtdclk real-time debugger port 7 p70/bclk/wr port 7 p82/txd0 p83/rxd0 p84/sclki0/sclko0 p85/txd1 p86/rxd1 p87/sclki1/sclko1 serial i/o port 8 16 ad1in0-ad1in15 a-d converter p67/adtrg avcc0, avcc1 avss0, avss1 port 6 p61-p63 port 6 avref0, avref1 vdd fvcc fp vcce 7 p174/txd2 p175/rxd2 p176/txd3 p177/rxd3 port 17 3.3v (note 1) 5v 3.3v 5v 3.3v 3.3v 5v note 1: : operates with a 3.3v power supply. : operates with a 3.3v or 5v power supply. 16 ad0in0-ad0in15 2 2 2 p200/txd4 p201/rxd4 p202/txd5 p203/rxd5 port 20 p220/ctx p221/crx can jtms jtck jtrst jtdo jtag jtdi port 22 p222, p223 port 22 p224/a11 (note 2) p225/a12 (note 2) note 2: use caution when using this port because it has a debug event function. p65/sclki4/sclko4 p64/sbi port 6 p66/sclki5/sclko5 port 6 3 8 trclk trsync trdata jdbi jevento jevent1 debug note 3: 255fbga is currently under development.
mitsubishi microcomputers 10 2001-5-14 rev.1.0 single-chip 32-bit cmos microcomputer 32170 group, 32174 group table 5 description of pin function (1/5 ) type pin name description input/output function power vcce power supply supplies power (5 v or 3.3v) to external i/o ports. supply vcci power supply supplies power (3.3 v) to the internal logic. vdd ram power supply nternal ram backup power supply (3.3 v). fvcc fl ash power supply internal flash memory backup power supply (3.3 v). vss ground connect all vss pins to ground (gnd). clock xin, clock input clock input/output pins. these pins contain a pll-based xout output frequency multiply-by-4, so input the clock whose frequency is quarter the operating frequency. (xin input = 10 mhz when cpu clock operates at 40 mhz) bclk / system clock output when this signal is system clock(bclk), it outputs a clock whose is twice that of ______ wr external inpout clock. (bclk output = 20 mhz when cpu clock operates at 40 mhz). use this clock when circuits are synchronized externally. ______ when this signal is write(wr),during external write access it indicates the valid data on the data bus to transfer. osc-vcc power supply power supply to the pll circuit. connect osc-vcc to the power supply(3.3v) osc-vss ground connect osc-vss to ground. vcnt pll control input this pin controls the pll circuit. connect a resistor and capacitor to this pin. reset ______ reset reset input this pin resets the internal circuits. mode mod0 mode input these pins set an operation mode. mod1 mod0 mod1 mode 0 0 single-chip mode 0 1 expanded external mode 1 0 processor mode 0 0 (boot mode) (note) 1 1 (reserved) address a11-a30 address output 20 lines of address bus (a11-a30) are provided to accommodate two bus bus channels of 2 mb memory space (max.) connected external to the chip. a31 is not output. in the write cycle, of the 16-bit data bus the valid byte positions to write are _________ ________ ________ _______ output as bhw/ bhe and blw/ ble. in read cycle, data on the entire 16-bit data bus is read. however, only the data at the valid byte positions are transferred to the m32rs internal circuit. data bus db0-db15 data bus input/output this 16-bit data bus connects to external device. note: fp pin should be h level in boot mode.
mitsubishi microcomputers 11 single-chip 32-bit cmos microcomputer 2001-5-14 rev.1.0 32170 group, 32174 group table 6 description of pin function (2/5) type pin type description input/output function bus ___ cs0, chip output chip select signals for external devices. control cs1 select __ rd read output this signal is output when reading external devices. ___ _______ bhw/ bhe byte high output indicates the byte positions to which valid are transferred when writing to write ________ _______ ________ _______ external devices.bhw/ bhe and blw/ ble correspond to the upper address ___ _______ blw/ ble byte low output side(d0-d7 effective) and the lower address side(d8-d15 effective),respectivel. write ____ wait wait input _________ if wait input is low when the m32r accesses external devices, the wait cycle extended. _____ hreq hold input this pin is used by an external device to request control of the external bus. request __________ the m32r goes to a hold state when hreq input is pulled low. ____ hack hold output this signal indicates to the external device that the m32r has entered a hold acknowledge state and relinquished control of the external bus. multijunction tin0 timer input input input pins for multijunction timer. timer -tin33 to0 timer output output output pins for multijunction timer. -to44 tclk0 timer clock input clock i nput pins for multijunction timer. -tclk3 a-d avcc0, analog power C avcc0 is the power supply for the a-d0 converters. avcc1 is the power converter avcc1 upply supply for the a-d1 converters. connect avcc0 and avcc1 to the power supply (5v or 3.3v). avss0, analog ground C avss0 is the analog ground for the a-d0 converters. avss1 is the avss1 analog ground for the a-d1 converters. connect avcc0 and avcc1 to ground. ad0in0 analog input input one block of 16-channel analog input pin for a-d0 converter. -ad0in15 ad1in0 two blocks of 16-channel analog input pin for a-d1 converter. -ad1in15 vref0, reference input vref0 is the reference voltage input pin (5v or 3.3v) for the a-d0 converters. vref1 voltage input vref1 is the reference voltage input pin (5v or 3.3v) for the a-d1 converters. _____ adtrg conversion input hardware trigger input pin to start a-d conversion. trigger interrupt ___ sbi systeminput system break interrupt(sbi) input pin of the interrupt controller. controller break interrupt
mitsubishi microcomputers 12 2001-5-14 rev.1.0 single-chip 32-bit cmos microcomputer 32170 group, 32174 group table 7 description of pin functions (3/5) type pin name description input/output function serial sclki0/ uart transmit/ input/output when channel 0 is in uart mode: i/o sclko0 receive clock clock output derived from brg output by dividing it by 2 output or csio transmit/receive when channel 0 is in csio mode: clock transmit/receive clock input when external clock is selected input/output transmit/receive clock output when internal clock is selected sclki1/ uart transmit/ input/output when channel 1 is in uart mode: sclko1 receive clock clock output derived from brg output by dividing it by 2 output or csio transmit/receive when channel 1 is in csio mode: clock transmit/receive clock input when external clock is selected input/output transmit/receive clock output when internal clock is selected sclki4/ uart transmit/ input/output when channel 4 is in uart mode: sclko4 receive clock clock output derived from brg output by dividing it by 2 output or csio transmit/receive when channel 4 is in csio mode: clock transmit/receive clock input when external clock is selected input/output transmit/receive clock output when internal clock is selected sclki5 uart transmit/ input/output when channel 5 is in uart mode: sclko5 receive clock clock output derived from brg output by dividing it by 2 output or csio transmit/receive when channel 5 is in csio mode: clock transmit/receive clock input when external clock is selected input/output transmit/receive clock output when internal clock is selected txd0 transmit data outpt transmit data output pin for serial i/o channel 0 rxd0 receive data input receive data input pin for serial i/o channel 0 txd1 transmit data output transmit data output pin for serial i/o channel 1 rxd1 receive data input receive data input pin for serial i/o channel 1 txd2 transmit data output transmit data output pin for serial i/o channel 2 rxd2 receive data input receive data input pin for serial i/o channel 2 txd3 transmit data output transmit data output pin for serial i/o channel 3 rxd3 receive data input receive data input pin for serial i/o channel 3 txd4 transmit data output transmit data output pin for serial i/o channel 4 rxd4 receive data input receive data input pin for serial i/o channel 4 txd5 transmit data output transmit data output pin for serial i/o channel 5 rxd5 receive data input receive data input pin for serial i/o channel 5
mitsubishi microcomputers 13 single-chip 32-bit cmos microcomputer 2001-5-14 rev.1.0 32170 group, 32174 group table 8 description of pin functions (4/5) type pin name description input/output function real-time rtdtxd transmit data output serial data output pin of the real-time debugger debugger rtdrxd receive data input serial data input pin of the real-time debugger rtdclk clock input input serial data transmit/receive clock input pin of the real-time debugger rtdack acknowledge output this pin outputs a low pulse synchronously with the real-time debuggers first clock of serial data output word. the low pulse width indicates the type of the command/data the realtime debugger has received. flash- fp flash protect input this pin protects the flash memory against e/w in hardware. only can ctx transmit data output data output pin from can module. crx receive data input data input pin to can module. jtag jtms test mode input test select input for controlling the test circuits state transition jtck clock input clock input to the debugger module and test circuit. jtrst test reset input test reset input for initializing the test circuit asynchronously. jtdo serial output output serial output of test instruction code or test data. jtdi serial input input serial input of test instruction code or test data. p00-p07 input/output port 0 input/output programmable input/output port. p10-p17 input/output port 1 input/output programmable input/output port. p20-p27 input/output port 2 input/output programmable input/output port. p30-p37 input/output port 3 input/output programmable input/output port. p41-p47 input/output port 4 input/output programmable input/output port. p61-p67 input/output port 6 input/output programmable input/output port. (however, p64 is an input-only port) p70-p77 input/output port 7 input/output programmable input/output port. p82-p87 input/output port 8 input/output programmable input/output port. p93-p97 input/output port 9 input/output programmable input/output port. p100 input/output port 10 input/output programmable input/output port. -p107 note: input/output port 5 is reserved for future use. input/ output port (note)
mitsubishi microcomputers 14 2001-5-14 rev.1.0 single-chip 32-bit cmos microcomputer 32170 group, 32174 group table 9 description of pin functions (5/5) type pin name description input/output function p110 input/output port 11 input/output programmable input/output port. -p117 p124 input/output port 12 input/output programmable input/output port. -p127 p130 input/output port 13 input/output programmable input/output port. -p137 p140 input/output port 14 input/output programmable input/output port. -p147 p150 input/output port 15 input/output programmable input/output port. -p157 p160 input/output port 16 input/output programmable input/output port. -p167 p172 input/output port 17 input/output programmable input/output port. -p177 p180 input/output port 18 input/output programmable input/output port. -p187 p190 input/output port 19 input/output programmable input/output port. -p197 p200 input/output port 20 input/output programmable input/output port. -p203 p210 input/output port 21 input/output programmable input/output port. -p217 p220 input/output port 22 input/output programmable input/output port. (note) -p225 (however, p221 is an input-only port) note: use caution when using p224 and p225 because they have a debug event function. input/ output port
mitsubishi microcomputers 15 single-chip 32-bit cmos microcomputer 2001-5-14 rev.1.0 32170 group, 32174 group figure 6 address space of the m32170f6 boot rom area (8k bytes) h'0000 0000 h'ffff ffff < logical space of the m32170f6 > h'7fff ffff h'8000 0000 user space eit vector entry logical address h'bfff ffff h'c000 0000 boot program space system space (16m bytes) h'0000 0000 h'00ff ffff h'007f ffff h'0080 0000 sfr area (16k bytes) h'0080 3fff h'0080 4000 h'001f ffff h'0020 0000 h'003f ffff h'0040 0000 internal rom area 768k bytes expanded external area (4m bytes) ghost area in units of 128k bytes 1g bytes 1g bytes 2g bytes ghost area in units of 16m bytes ghost area in units of 4m bytes internal ram (40k bytes) h'0080 dfff h'8000 0000 h'8000 1fff ghost area in units of 16k bytes reserved area (8k bytes) reserved area (72k bytes) h'0081 ffff h'0082 0000 h'0080 e000 h'8000 3fff h'8000 2000 h'8000 4000 h'bfff ffff h'000b ffff h'0010 0000 cs1 area cs0 area reserved area (256k bytes) h'000f ffff
mitsubishi microcomputers 16 2001-5-14 rev.1.0 single-chip 32-bit cmos microcomputer 32170 group, 32174 group figure 7 address space of the m32170f4 boot rom area (8k bytes) h'0000 0000 h'ffff ffff < logical space of the m32170f4 > h'7fff ffff h'8000 0000 user space eit vector entry logical address h'bfff ffff h'c000 0000 boot program space system space (16m bytes) h'0000 0000 h'00ff ffff h'007f ffff h'0080 0000 sfr area (16k bytes) h'0080 3fff h'0080 4000 h'001f ffff h'0020 0000 h'003f ffff h'0040 0000 internal rom area 512k bytes expanded external area (4m bytes) 1g bytes 1g bytes 2g bytes ghost area in units of 16m bytes ghost area in units of 4m bytes internal ram (32k bytes) h'0080 bfff h'8000 0000 h'8000 1fff reserved area (8k bytes) reserved area (80k bytes) h'0081 ffff h'0082 0000 h'0080 c000 h'8000 3fff h'8000 2000 h'8000 4000 h'bfff ffff h'0007 ffff h'0010 0000 cs1 area cs0 area reserved area (512k bytes) h'000f ffff ghost area in units of 16k bytes ghost area in units of 128k bytes
mitsubishi microcomputers 17 single-chip 32-bit cmos microcomputer 2001-5-14 rev.1.0 32170 group, 32174 group figure 8 address space of the m32170f3 boot rom area (8k bytes) h'0000 0000 h'ffff ffff < logical space of the m32170f3 > h'7fff ffff h'8000 0000 user space eit vector entry logical address h'bfff ffff h'c000 0000 boot program space system space (16m bytes) h'0000 0000 h'00ff ffff h'007f ffff h'0080 0000 sfr area (16k bytes) h'0080 3fff h'0080 4000 h'001f ffff h'0020 0000 h'003f ffff h'0040 0000 internal rom area 384k bytes expanded external area (4m bytes) ghost area in units of 128k byt e 1g bytes 1g bytes 2g bytes ghost area in units of 4m bytes internal ram (32k bytes) h'0080 bfff h'8000 0000 h'8000 1fff ghost area in units of 16k bytes reserved area (8k bytes) reserved area (80k bytes) h'0081 ffff h'0082 0000 h'0080 c000 h'8000 3fff h'8000 2000 h'8000 4000 h'bfff ffff h'0005 ffff h'0010 0000 cs1 area cs0 area reserved area (640k bytes) h'000f ffff ghost area in units of 16m bytes
mitsubishi microcomputers 18 2001-5-14 rev.1.0 single-chip 32-bit cmos microcomputer 32170 group, 32174 group boot rom area (8k bytes) h'0000 0000 h'ffff ffff < logical space of the m32174f4 > h'7fff ffff h'8000 0000 user space eit vector entry logical address h'bfff ffff h'c000 0000 boot program space system space (16m bytes) h'0000 0000 h'00ff ffff h'007f ffff h'0080 0000 sfr area (16k bytes) h'0080 3fff h'0080 4000 h'001f ffff h'0020 0000 h'003f ffff h'0040 0000 internal rom area 512k bytes expanded external area (4m bytes) 1g bytes 1g bytes 2g bytes ghost area in units of 16m bytes ghost area in units of 4m bytes internal ram (40k bytes) h'0080 dfff h'8000 0000 h'8000 1fff ghost area in units of 16k bytes reserved area (8k bytes) reserved area (72k bytes) h'0081 ffff h'0082 0000 h'0080 e000 h'8000 3fff h'8000 2000 h'8000 4000 h'bfff ffff h'0007 ffff h'0010 0000 cs1 area cs0 area reserved area (512 bytes) h'000f ffff ghost area in units of 128k bytes figure 9 address space of the m32174f4
mitsubishi microcomputers 19 single-chip 32-bit cmos microcomputer 2001-5-14 rev.1.0 32170 group, 32174 group figure 10 address space of the m32174f3 boot rom area (8k bytes) h'0000 0000 h'ffff ffff < logical space of the m32174f3 > h'7fff ffff h'8000 0000 user space eit vector entry logical address h'bfff ffff h'c000 0000 boot program space system space (16m bytes) h'0000 0000 h'00ff ffff h'007f ffff h'0080 0000 sfr area (16k bytes) h'0080 3fff h'0080 4000 h'001f ffff h'0020 0000 h'003f ffff h'0040 0000 internal rom area 384k bytes expanded external area (4m bytes) ghost area in units of 128k bytes 1g bytes 1g bytes 2g bytes ghost area in units of 16m bytes ghost area in units of 4m bytes internal ram (40k bytes) h'0080 dfff h'8000 0000 h'8000 1fff ghost area in units of 16k bytes reserved area (8k bytes) reserved area (72k bytes) h'0081 ffff h'0082 0000 h'0080 e000 h'8000 3fff h'8000 2000 h'8000 4000 h'bfff ffff h'0005 ffff h'0010 0000 cs1 area cs0 area reserved area (640k bytes) h'000f ffff
mitsubishi microcomputers 20 2001-5-14 rev.1.0 single-chip 32-bit cmos microcomputer 32170 group, 32174 group figure 11 sfr area h'0080 0000 h'0080 007e h'0080 0180 interrupt controller (icu) h'0080 0080 a-d0 converter h'0080 00ee serial i/o h'0080 0100 h'0080 0146 wait controller mjt (common part) mjt (top) mjt (tio) mjt (tms) h'0080 0200 h'0080 0240 h'0080 0300 h'0080 03c0 h'0080 03e0 h'0080 03fe note: the real-time debugger (rtd) is an independent module operated from external circuits, and is transparent to the cpu. +0 address +1 address 0 7 8 15 h'0080 0a00 to to to to to to to to +0 address +1 address 0 7 8 15 multijunction timer (mjt) flash control h'0080 07e0 h'0080 07f2 h'0080 023e h'0080 02fe mjt (tod0) h'0080 078c h'0080 07de to mjt (tid0) h'0080 0790 h'0080 078e multijunction timer (mjt) serial i/o h'0080 0a26 h'0080 0a80 a-d1 converter h'0080 0aee mjt (tod1) mjt (tom) h'0080 0bde h'0080 0c8c h'0080 0cde mjt (tml1) h'0080 0fe0 h'0080 0ffe multijunction timer (mjt) h'0080 0400 dmac h'0080 0478 to can h'0080 1000 h'0080 11fe h'0080 0700 input/output ports h'0080 077e to h'0080 03be h'0080 03d8 mjt (tml0) h'0080 0b8c mjt (tid1) h'0080 0b8e h'0080 0b90 h'0080 0c8e h'0080 0c90 mjt (tid2) to to to to to to to h'0080 3ffe
mitsubishi microcomputers 21 single-chip 32-bit cmos microcomputer 2001-5-14 rev.1.0 32170 group, 32174 group built-in flash memory and ram 32170 and 32174 group contain flash memory and ram stated as follows. the internal flash memory can be programmed on-board (i.e., while being mounted on the printed circuit board). this means that the same chip as will be used in mass-produc- tion can be used directly from the development stage on, allowing for system development without having to change the printed circuit board when proceeding from trial produc- tion to mass-production. table 10 flash memory and ram size (32170 group) type name rom size ram size m32170f6vfp 768k bytes 40k bytes m32170f4vfp 512k bytes 32k bytes m32170f3vfp 384k bytes 32k bytes m32170f6vwg 768k bytes 40k bytes m32170f4vwg 512k bytes 32k bytes m32170f3vwg 384k bytes 32k bytes table 11 flash memory and ram size (32174 group) type name rom size ram size m32174f4vfp 512k bytes 40k bytes m32174f3vfp 384k bytes 40k bytes m32174f4vwg 512k bytes 40k bytes m32174f3vwg 384k bytes 40k bytes built-in virtual-flash emulation function internal flash memory, which is divided from the first address in units of 8 kbyte (l banks), can be replaced in 8 -kbyte blocks (h70080 4000-h0080 5fff) of the internal ram. and also the internal flash memory, which is divided from the first address in units of 4-kbyte areas (s banks), can be re- placed in 4 kbytes areas. this function allows parts of the program which are fre- quently changed during development to be altered or evalu- ated without having to reset the microcomputer each time. whats more, when combined with the realtime debugger, this function helps to reduce the program evaluation period, because data in the ram can be rewritten without requiring any cpu load.
mitsubishi microcomputers 22 2001-5-14 rev.1.0 single-chip 32-bit cmos microcomputer 32170 group, 32174 group h'0000 0000 h'0000 2000 h'0006 6000 < internal flash > < internal ram > l bank 1 (8k bytes) h'0080 4000 h'0080 6000 l bank 0 (8k bytes) h'0000 4000 h'0006 4000 l bank 51 (8k bytes) l bank 50 (8k bytes) l bank 2 (8k bytes) 8k bytes 8k bytes 8k bytes 8k bytes l bank 95 (8k bytes) l bank 94 (8k bytes) h'000b e000 h'000b c000 h'0080 8000 h'0080 a000 4k bytes 4k bytes h'0000 0000 h'0000 1000 < internal flash > < internal ram > s bank 1 (4k bytes) h'0080 4000 s bank 0 (4k bytes) h'0000 2000 s bank 2 (4k bytes) 8k bytes s bank 191 (4k bytes) s bank 190 (4k bytes) h'000b f000 h'000b e000 8k bytes 8k bytes 8k bytes 4k bytes 4k bytes h'0080 c000 h'0080 d000 figure 12 virtual-flash emulation areas of the m32170f6vfp (replaced in units of 8 kbytes) note 1: if the same bank area is set in multiple virtual-flash bank registers and the virtual-flash emulation enable bit is ena bled, the corresponding internal ram area is assigned to either bank register according to the priority felbank0 > felban k1 > felbank2 > felbank3 > fesbank0 > fesbank1. note 2: when access is made to the 8-kbyte area (l bank) specified with virtual-flash bank registers 0-3, the internal ram area is accessed. during virtual-flash emulation mode, ram data can read and written to and from both the internal ram area and the virtual-flash setup area. figure 13 virtual-flash emulation areas of the m32170f6vfp (replaced in units of 4 kbytes) note 1: if the same bank area is set in multiple virtual-flash bank registers and the virtual-flash emulation enable bit is ena bled, the corresponding internal ram area is assigned to either bank register according to the priority felbank0 > felban k1 > felbank2 > felbank3 > fesbank0 > fesbank1. note 2: when access is made to the 4-kbyte area (s bank) specified with virtual-flash bank registers 0 and 1, the internal ram area is accessed. during virtual-flash emulation mode, ram data can read and written to and from both the internal ram area and the virtual-flash setup area.
mitsubishi microcomputers 23 single-chip 32-bit cmos microcomputer 2001-5-14 rev.1.0 32170 group, 32174 group figure 14 virtual-flash emulation areas of the m32170f4vfp (replaced in units of 8 kbytes) note 1: if the same bank area is set in multiple virtual-flash bank registers and the virtual-flash emulation enable bit is ena bled, the corresponding internal ram area is assigned to either bank register according to the priority felbank0 > felban k1 > felbank2 > fesbank0 > fesbank1. note 2: when access is made to the 8-kbyte area (l bank) specified with virtual-flash bank registers 0-2, the internal ram area is accessed. during virtual-flash emulation mode, ram data can read and written to and from both the internal ram area and the virtual-flash setup area. h'0000 0000 h'0000 2000 < internal flash > l bank 1 (8k bytes) l bank 0 (8k bytes) h'0000 4000 l bank 2 (8k bytes) l bank 63 (8k bytes) l bsnk 62 (8k bytes) h'0007 e000 h'0007 c000 < internal ram > 8k bytes 8k bytes 8k bytes 4k bytes 4k bytes h'0080 4000 h'0080 6000 h'0080 8000 the table below shows virtual-flash emulation areas of the m32170f4 and m32170f3. table 12 virtual-flash emulation areas of the m32170f4 and m32170f3 type virtual-flash emulation areas m32170f4vfp,m32170f4vwg h 0000 0000 - h 0007 ffff m32170f3vfp,m32170f3vwg h 0000 0000 - h 0005 ffff figure 15 virtual-flash emulation areas of the m32170f4vfp (replaced in units of 4 kbytes) note 1: if the same bank area is set in multiple virtual-flash bank registers and the virtual-flash emulation enable bit is ena bled, the corresponding internal ram area is assigned to either bank register according to the priority felbank0 > felban k1 > felbank2 > fesbank0 > fesbank1. note 2: when access is made to the 4-kbyte area (s bank) specified with virtual-flash bank registers 0 and 1, the internal ram area is accessed. during virtual-flash emulation mode, ram data can read and written to and from both the internal ram area and the virtual-flash setup area. h'0000 0000 h'0000 1000 < internal flash > < internal ram > s bank 1 (4k bytes) h'0080 4000 s bank 0 (4k bytes) h'0000 2000 s bank 2 (4k bytes) 8k bytes s bank 127 (4k bytes) s bank 126 (4k bytes) h'0007 f000 h'0007 e000 8k bytes 8k bytes 4k bytes 4k bytes h'0080 a000 h'0080 b000
mitsubishi microcomputers 24 2001-5-14 rev.1.0 single-chip 32-bit cmos microcomputer 32170 group, 32174 group figure 16 virtual-flash emulation areas of the m32174f4vfp (replaced in units of 8 kbytes) note 1: if the same bank area is set in multiple virtual-flash bank registers and the virtual-flash emulation enable bit is ena bled, the corresponding internal ram area is assigned to either bank register according to the priority felbank0 > felban k1 > felbank2 > fesbank0 > fesbank1. note 2: when access is made to the 8-kbyte area (l bank) specified with virtual-flash bank registers 0-2, the internal ram area is accessed. during virtual-flash emulation mode, ram data can read and written to and from both the internal ram area and the virtual-flash setup area. note 3: internal ram area (h0080 c000-h0080 dfff) cannot be used as virtual flash emulation area. the table below shows virtual-flash emulation areas of the m32174f4 and m32174f3. table 13. virtual-flash emulation areas of the m32174f4 and m32174f3 type name virtual-flash emulation areas m32174f4vfp,m32174f4vwg h 0000 0000 - h 0007 ffff m32174f3vfp,m32174f3vwg h 0000 0000 - h 0005 ffff h'0000 0000 h'0000 2000 < internal flash > l bank 1 (8k bytes) l bank 0 (8k bytes) h'0000 4000 l bank 2 (8k bytes) l bank 63 (8k bytes) l bank 62 (8k bytes) h'0007 e000 h'0007 c000 < internal ram > 8k bytes 8k bytes 8k bytes 8k bytes 4k bytes 4k bytes h'0080 4000 h'0080 6000 h'0080 8000 h'0080 c000 h'0080 dfff figure 17 virtual-flash emulation areas of the m32174f4vfp (replaced in units of 4 kbytes) note 1: if the same bank area is set in multiple virtual-flash bank registers and the virtual-flash emulation enable bit is ena bled, the corresponding internal ram area is assigned to either bank register according to the priority felbank0 > felban k1 > felbank2 > fesbank0 > fesbank1. note 2: when access is made to the 4-kbyte area (s bank) specified with virtual-flash bank registers 0 and 1, the internal ram area is accessed. during virtual-flash emulation mode, ram data can read and written to and from both the internal ram area and the virtual-flash setup area. note 3: internal ram area (h0080 c000-h0080 dfff) cannot be used as virtual flash emulation area. h'0000 0000 h'0000 1000 < internal flash > < internal ram > s bank 1 (4k bytes) h'0080 4000 s bank 0 (4k bytes) h'0000 2000 s bank 2 (4k bytes) 8k bytes s bank 127 (4k bytes) s bank 126 (4k bytes) h'0007 f000 h'0007 e000 8k bytes 8k bytes 8k bytes 4k bytes 4k bytes h'0080 a000 h'0080 b000 h'0080 c000 h'0080 dfff
mitsubishi microcomputers 25 single-chip 32-bit cmos microcomputer 2001-5-14 rev.1.0 32170 group, 32174 group input/output ports the microcomputer has a total of 157 input/output ports p0-p22. (however, p5 is reserved for future use.) the input/ output ports can be used as input ports or output ports by setting up their direction registers. each input/output port is a dual-function pin shared with table 14 outline of input/output ports item specification number of port total 157 ports p0 : p00 - p07 (8 lines) p1 : p10 - p17 (8 lines) p2 : p20 - p27 (8 lines) p3 : p30 - p37 (8 lines) p4 : p41 - p47 (7 lines) p6 : p61 - p67 (7 lines) p7 : p70 - p77 (8 lines) p8 : p82 - p87 (6 lines) p9 : p93 - p97 (5 lines) p10 : p100 - p107 (8 lines) p11 : p110 - p117 (8 lines) p12 : p124 - p127 (4 lines) p13 : p130 - p137 (8 lines) p14 : p140 - p147 (8 lines) p15 : p150 - p157 (8 lines) p16 : p160 - p167 (8 lines) p17 : p172 - p177 (6 lines) p18 : p180 - p187 (8 lines) p19 : p190 - p197 (8 lines) p20 : p200 - p203 (4 lines) p21 : p210 - p217 (8 lines) p22 : p220 - p225 (6 lines) port function the input/output ports can be set for input or output mode bitwise by using the input/output port ___ direction control register. (however, p64 is an sbi input-only port, and p221 is can input-only port.) pin function dual-functions shared with peripheral i/o or external extended signals (or multi-functions shared with peripheral i/os which have multiple functions.) pin function p0-4, p225, p225 : changed by setting cpu operation mode (mod0 and mod1 pins) changeover p6-22 : changed by setting the input/output port operation mode register. (however, peripheral i/o pin functions are selected using the peripheral i/o register.) table 15 cpu operation modes and p0-p4, p224, and p225 pin functions mod0 mod1 operation mode pin functions of p0-p4, p224, p225 vss vss single-chip mode nput/output port pin vss vcce external extended mode vcce vss processor mode (fp pin = vss) vcce vcc reserved (use inhibited) C note: vcc and vss are connected to +5 v and gnd, respectively. otherinternal peripheral i/o or external extended bus signal lines. these pin functions are selected by using the chip op- eration mode select or the input/output port operation mode registers. these input/output ports are interfaced using a dedicated power supply to allow for connections to the pe- ripheral circuits operating with 5v or 3.3v. external extended signal pin
mitsubishi microcomputers 26 2001-5-14 rev.1.0 single-chip 32-bit cmos microcomputer 32170 group, 32174 group figure 18 input/output ports and pin function assignments p0 p1 p2 p3 p4 p6 p7 p8 p9 p10 p11 p12 p13 p14 p15 p5 db0 01 234 567 db1 db2 db3 db4 db5 db6 db7 db8 db9 db10 db11 db12 db13 db14 db15 a23 a24 a25 a26 a27 a28 a29 a30 a15 a16 a17 a18 a19 a20 a21 a22 blw bhw rd cs0 cs1 a13 a14 (p61) (p62) (p63) sbi sclki4/ sclko4 adtrg bclk wait hreq hack rtdtxd rtdrxd rtdack rtdclk txd0 rxd0 sclki0/ sclko0 txd1 rxd1 sclki1/ sclko1 to16 to17 to18 to19 to20 to11 to12 to13 to14 to15 to10 to9 to8 to3 to4 to5 to6 to7 to2 to1 to0 tclk0 tclk1 tclk2 tclk3 tin16 tin17 tin18 tin19 tin20 tin21 tin22 tin23 tin8 tin9 tin10 tin11 tin12 tin13 tin14 tin15 tin0 tin1 tin2 tin3 tin4 tin5 tin6 tin7 cpu operation mode settings (note1) (reserved) input/output port operation mode register settings note 1: the pin function are selected by setting the mod0 and mod1 pins. note 2: the pin function are selected by setting the mod0 and mod1 pins. also, use of this pin requires caution because it has a debug event function. p16 to21 to22 to23 to24 to25 to26 to27 to28 p17 tin24 tin25 txd2 rxd2 txd3 rxd3 p18 p19 to29 to30 to31 to32 to33 to34 to35 to36 p20 txd4 rxd4 rxd5 p21 to37 to38 to39 to40 to41 to42 to43 to44 p22 ctx crx (p222) (p223) a11 (note2) a12 (note2) tin26 tin27 tin28 tin29 tin30 tin31 tin32 tin33 txd5 sclki5/ sclko5
mitsubishi microcomputers 27 single-chip 32-bit cmos microcomputer 2001-5-14 rev.1.0 32170 group, 32174 group item content number of channels 10 channels transfer request ? software trigger ? request from internal peripheral i/o: a-d converter, multijunction timer, or serial i/o (reception completed, transmit buffer empty) ? cascaded connection between dma channels possible (note) maximum number of times transferred 256 times transferable address space ? 64 kbytes (address space from h0080 0000 to h0080 ffff) ? transfers between internal peripheral i/os, between internal ram and internal peripheral io, and between internal rams are supported transfer data size 16 bits or 8 bits transfer method single transfer dma (control of the internal bus is relinquished for each transfer performed), dual-address transfer transfer mode single transfer mode direction of transfer one of three modes can be selected for the source and destination of transfer: ? address fixed ? address increment ? 32-channel ring buffer channel priority channel 0 > channel 1 > channel 2 > channel 3 > channel 4 > channel 5 > channel 6 > channel 7 > channel 8 > channel 9 (fixed priority) maximum transfer rate 13.3 mbytes per second (when internal peripheral clock = 20 mhz) interrupt request group interrupt request can be generated when each transfer count register underflows transfer area 64 kbytes from h0080 0000 to h0080 ffff (transfer is possible in the entire internal ram/sfr area) note: the following dma channels can be cascaded. dma transfer on channel 1 started at end of one dma transfer on channel 0 dma transfer on channel 2 started at end of one dma transfer on channel 1 dma transfer on channel 0 started at end of one dma transfer on channel 2 dma transfer on channel 4 started at end of one dma transfer on channel 3 dma transfer on channel 6 started at end of one dma transfer on channel 5 dma transfer on channel 7 started at end of one dma transfer on channel 6 dma transfer on channel 5 started at end of one dma transfer on channel 7 dma transfer on channel 9 started at end of one dma transfer on channel 8 dma transfer on channel 5 started at end of all dma transfers on channel 0 (underflow of transfer count register) built-in 10-channel dmac the microcomputer contains 10 channels of dmac, allowing for data transfer between internal peripheral i/os, between internal ram and internal peripheral i/o, and between inter- nal rams. dma transfer requests can be issued from the user-cre ated software, as well as can be triggered by a signal gener- ated by the internal peripheral i/o (a-d converter, mjt, or serial i/o). table 16 outline of the dmac the microcomputer also supports cascaded connection be- tween dma channels (starting dma transfer on a channel at end of transfer on another channel). this makes advanced transfer processing possible without causing any additional cpu load.
mitsubishi microcomputers 28 2001-5-14 rev.1.0 single-chip 32-bit cmos microcomputer 32170 group, 32174 group figure 19 block diagram of the dmac dma channel 8 source destination transfer count udf source destination transfer count udf udf dma channel 2 udf dma request selector dma request selector a-d0 conversion completed dma channel 0 software start mjt (tin13 input signal) one dma0 transfer completed internal bus software start software start serial i/o0 (reception completed) interrupt request one dma2 transfer completed mjt (tio8_udf) mjt (input event bus 2) mjt (output event bus 0) mjt (tin19 input signal) software start mjt (tin18 input signal) one dma1 transfer completed mjt (output event bus 0) software start serial i/o0 (transmit buffer empty) serial i/o1 (reception completed) dma channel 1 dma channel 3 dma channel 4 determination block transfer count udf dma start mjt (tin0 input signal) all dma0 transfer completed (udf) software start mjt (tin1 input signal) one dma5 transfer completed software start software start serial i/o3 (transmit buffer empty) one dma7 transfer completed one dma8 transfer completed serial i/o2 (reception completed) mjt (tin20 input signal) serial i/o1 (transmit buffer empty) mjt (tin8 input signal) software start mjt (tin2 input signal) one dma6 transfer completed serial i/o2 (transmit buffer empty) software start mjt (intput event bus 0) serial i/o3 (reception completed) mjt (tin7 input signal) udf dma channel 7 dma channel 5 interrupt request dma channel 6 dma channel 9 determination block dma start internal bus arbitration dma request selector udf dma request selector source destination transfer count udf source destination transfer count udf dma request selector source destination transfer count udf internal bus arbitration dma request selector dma request selector dma request selector dma request selector dma request selector one dma3 transfer completed destination source source source source source destination destination destination destination transfer count transfer count transfer count transfer count
mitsubishi microcomputers 29 single-chip 32-bit cmos microcomputer 2001-5-14 rev.1.0 32170 group, 32174 group built-in 64-channel multijunction timers (mjt) the microcomputer contains a total of 64 channels of multijunction timers consisting of 35 channels of 16-bit out- put related timers, 10 channels of 16-bit input/output related timers, 11 channels of 16-bit input related timers, eight chan- nels of 32-bit input related timers. each timer has multiple operation modes to choose from, depending on the pur- poses of use. also, the maltijunction timers internally have a clock bus, in- put event bus, and an output event bus, so that multiple tim- ers can be used in combination allowing for a flexible timer configuration. the output related timers have a correcting function that allows the timers count value to be incremented or decremented as necessary while count is in progress, mak- ing real time output control possible. timer clk en e/ l prs clock bus input event bus e/l timer clk en interrupt output interrupt output output event bus f/f to pin tin pin tclk pin note: this is a conceptual diagram and does not show the actual timer configuration. e/l prs : edge/level selector : prescaler : junction box (selector) : output flip-flop f/ f to dmac, a-d converter f/f to pin output related timer : 35ch input/output related timer : 10ch 16-bit input related timer : 11ch 32-bit input related timer : 8ch 1/2 internal peripheral clock figure 20 conceptual diagram of the multijunction timer (mjt)
mitsubishi microcomputers 30 2001-5-14 rev.1.0 single-chip 32-bit cmos microcomputer 32170 group, 32174 group table 17 outline of multijunction timers (1/2) name type number of channels content top output-related 11 one of three input modes can be selected in software. (timer output) 16-bit timer < with correction function > (down-counter) ? single-shot output mode ? delayed single-shot output mode < without correction function > ? continuous output mode tio input/output-related 10 one of three input modes or four output modes can be (timer 16-bit timer selected by software. input output) (down-counter) < input modes > ? measure clear input mode ? measure free-run input mode ? noise processing input mode < output mode without correction function ? pwm output mode ? single-shot output mod ? delayed single-shot output mode ? continuous output mode tms input-related 8 16-bit input measure timer. (timer 16-bit timer measure small) (up counter) tml input-related 8 32-bit input measure timer. (timer 32-bit timer measure large) (up counter) tid input-related 3 one of three input modes can be selected in software. (timer 16-bit timer ? fixed cycle mode input derivation) (up counter) ? event count mode ? multiply-by-4 event count mode
mitsubishi microcomputers 31 single-chip 32-bit cmos microcomputer 2001-5-14 rev.1.0 32170 group, 32174 group name type number of channels content tod output-related 16 one of four output modes can be selected in software. (timer 16-bit timer < no correction function > output modification) (down-counter) ? pwm output mode ? single-shot output mode ? delayed single-shot output mode ? continuous output mode tom output-related 8 one of four output modes can be selected in software. (timer 16-bit timer < no correction function > output modification) (down-counter) ? pwm output mode ? single-shot pwm output mode ? one-shot output mode ? continuous output mode table 18 outline of multijunction timers (2/2)
mitsubishi microcomputers 32 2001-5-14 rev.1.0 single-chip 32-bit cmos microcomputer 32170 group, 32174 group figure 21 block diagram of multijunction timers (mjt) (1/4) irq2 irq12 irq12 irq12 clk en udf top 0 clock bus input event bus clk en udf top 1 clk en udf top 2 clk en udf top 3 output event bus tclk0s to 0 irq9 3 2 1 0 1/2 internal peripheral clock irq8 clk en udf top 4 clk en udf top 5 tclk0 tin0 tin7 tclk1 s s tin0s clk en udf top 6 clk en udf top 7 s s s irq9 tin1 irq9 tin2 s s clk en udf top 8 clk en udf top 9 clk en udf top 10 clk en/cap udf tio 0 clk en/cap udf tio 1 clk en/cap udf tio 2 clk en/cap udf tio 3 clk en/cap udf tio 4 s s tin3 s s tin4 tin5 s s irq12 tin6 prs1 prs0 clk en/cap udf tio 5 s s irq8 tin8 tclk2 clk en/cap udf tio 6 s s irq8 tin9 clk en/cap udf tio 7 s s irq8 tin10 s s clk en/cap udf tio 8 clk en/cap udf tio 9 irq8 tin11 s s f/f0 f/f1 f/f2 f/f3 f/f4 f/f5 f/f6 f/f7 f/f8 f/f9 f/f10 f/f11 f/f12 f/f13 f/f14 f/f15 s f/f16 f/f17 f/f18 f/f19 f/f20 s : selector f/f : output flip-flop prs0-5 : prescaler s s s s s s s s s s s s s s irq2 irq2 irq2 irq2 irq2 to 1 to 2 to 3 to 4 to 5 to 6 to 7 to 8 to 9 to 10 to 11 to 12 to 13 to 14 to 15 irq1 irq1 irq6 irq6 irq5 irq0 irq0 irq0 irq0 irq4 to 16 to 17 to 18 to 19 to 20 irq4 drq0 irq3 irq3 3 2 1 0 0 1 2 3 3 2 1 0 3 2 1 0 prs2 irq4 irq4 0 1 2 3 tin1s tin2s tin3s tin4s tin5s tin6s tclk1s tclk2s tin7s tin8s tin9s tin10s tin11s drq7 drq8 drq9 drq10 drq11
mitsubishi microcomputers 33 single-chip 32-bit cmos microcomputer 2001-5-14 rev.1.0 32170 group, 32174 group figure 22 block diagram of multijunction timers (mjt) (2/4) clock bus input event bus 3 2 1 0 3 2 1 0 clk tms 0 s ovf cap3 cap2 cap1 cap0 s s s s tclk3 tclk3s drq3 irq10 tin12 tin13 tin14 tin15 clk tms 1 ovf cap3 cap2 cap1 cap0 s s s s s drq5 tin16 tin17 tin18 tin19 drq6 irq10 irq10 irq10 irq10 irq10 irq10 irq10 clk tml0 cap3 cap2 cap1 cap0 s s s s tin20 tin21 tin22 tin23 irq11 irq11 irq11 irq11 1/2 internal peripheral clock output event bus 0 1 2 3 irq7 irq7 3 2 1 0 3 2 1 0 0 1 2 3 tin12s tin13s tin14s tin15s tin16s tin17s tin18s tin19s tin20s tin21s tin22s tin23s s drq12 clk tml1 cap3 cap2 cap1 cap0 s s s s tin30 tin31 tin32 tin33 tin30s tin31s tin32s tin33s s irq18 irq18 irq18 irq18 1/2 internal peripheral clock s : serector ad0trg (to a-d converter) drq2 drq4
mitsubishi microcomputers 34 2001-5-14 rev.1.0 single-chip 32-bit cmos microcomputer 32170 group, 32174 group clock bus input event bus 3 2 1 0 3 2 1 0 output event bus 0 1 2 3 3 2 1 0 3 2 1 0 0 1 2 3 clk tid0 ovf udf tin24 tin25 1/2 internal peripheral clock irq14 clk tod0_0 udf f/f21 clk tod0_1 udf f/f22 to21 to22 clk tod0_2 udf f/f23 clk tod0_3 udf f/f24 to23 to24 clk tod0_4 udf f/f25 clk tod0_5 udf f/f26 to25 to26 clk tod0_6 udf f/f27 clk tod0_7 udf f/f28 to27 to28 irq13 irq13 irq13 irq13 irq13 irq13 irq13 irq13 clk1 clk2 prs3 clk tid1 tin26 tin27 1/2 internal peripheral clock irq15 clk tod1_0 udf f/f29 clk tod1_1 udf f/f30 to29 to30 clk tod1_2 udf f/f31 clk tod1_3 udf f/f32 to31 to32 clk tod1_4 udf f/f33 clk tod1_5 udf f/f34 to33 to34 clk tod1_6 udf f/f35 clk tod1_7 udf f/f36 to35 to36 irq16 irq16 irq16 irq16 irq16 irq16 irq16 irq16 clk1 clk2 prs4 en en en en en en clk tid2 tin28 tin29 1/2 internal peripheral clock clk tom0_0 udf f/f37 clk tom0_1 udf f/f38 to37 to38 clk tom0_2 udf f/f39 clk tom0_3 udf f/f40 to39 to40 clk tom0_4 udf f/f41 clk tom0_5 udf f/f42 to41 to42 clk tom0_6 udf f/f43 clk tom0_7 udf f/f44 to43 to44 irq16 irq16 irq16 irq16 irq16 irq16 irq16 irq16 clk1 clk2 prs5 en en en en en en en en ad1trg (to a-d converter ) ovf udf ovf udf irq17 en en figure 23 block diagram of multijunction timers (mjt) (3/4)
mitsubishi microcomputers 35 single-chip 32-bit cmos microcomputer 2001-5-14 rev.1.0 32170 group, 32174 group figure 24 block diagram of multijunction timers (mjt) (4/4) udf end clock bus input event bus 3 2 1 0 3 2 1 0 output event bus 0 1 2 3 3 2 1 0 3 2 1 0 0 1 2 3 ad0 completed tio8-udf s dma0 udf end dmairq0 s dma1 udf end dmairq0 tin13 udf tin18 s dma3 udf end dmairq0 s dma4 udf dmairq0 tin19 sio0-txd sio1-rxd sio0-rxd s dma5 udf end dmairq1 dmairq1 sio2-rxd sio1-txd dmairq1 dmairq1 sio2-txd sio3-rxd dmairq1 sio3-txd tin2 tin7 tin8 tin20 tin1 tin0 udf end s dma2 udf dmairq0 s dma6 udf end dma7 udf end s dma8 udf end s s dma9 udf s : selector
mitsubishi microcomputers 36 2001-5-14 rev.1.0 single-chip 32-bit cmos microcomputer 32170 group, 32174 group built-in two independent a-d converters the microcomputer contains two 16-channel converters with 10-bit resolution (a-d0 converter and a-d1 converter). in addition to single conversion on each channel, continuous a-d conversion on a combined group of 4, 8, and 16 chan- nels is possible. the a-d converted value can be read out in either 10 bits or 8 bits. table 19 outline of the a-d converters item content analog input 16 channels 2 a-d conversion method s uccessive approximation method. resolution 10 bits (conversion results can be read out in either 10 or 8 bits.) absolute accuracy (note 1) normal rate mode + 2 lsb (conditions: ta = -40 ~ +125 c, double rate mode + 2 lsb avcc0,1 = vref0,1 = 5.12v) conversion mode a-d conversion mode,comparator mode operation mode single mode, scan mode scan mode single -shot scan mode, continuous scan mode. conversion start trigger software start started by setting a-d conversion start bit to 1. hardware start a-d0 converter started by mjt output event bus 3, a-d1 converter started by tid1 overflow or underflow. _____ started by external adtrg pin input. conversion rate during single mode normal 299 1/ f (bclk) (note 2) f(bclk) : internal peripheral clock (shortest time ) double speed 173 1/ f (bclk) operating frequency during comparator mode normal 47 1/ f (bclk) (shortest time ) double speed 29 1/ f (bclk) interrupt request generation when a-d conversion is finished, when comparate operation is finished, when single-shot scan is finished, or when one cycle of continuous scan is finished. dma transfer request generation when a-d conversion is finished, when comparate operation is finished, when single-s hot (note 3) scan is finished, or when one cycle of continuous scan is finished. note 1: the rated value of conversion accuracy here is that of the microcomputer's own as a single unit which can be exhibited when the microcomputer is used in an environment where it may not be affected by the power supply wiring or noise on the boa rd. note 2: when bclk = 20 mhz, this is1/f (bclk) = 50ns. note 3: the dma transfer request generation function is available for only the a-d0 converter. the a-d1 converter does not have this function. in addition to ordinary a-d conversion, the converters sup- port comparator mode in which the set value and a-d con- verted value are compared to determine which is larger or smaller than the other. when a-d conversion is finished, the converters can generated a dma transfer request (a-d0 converter only), as well as an interrupt. the a-d converters are interfaced using a dedicated power supply to allow for connections to the peripheral circuits op- erating with 5 v or 3.3v.
mitsubishi microcomputers 37 single-chip 32-bit cmos microcomputer 2001-5-14 rev.1.0 32170 group, 32174 group figure 25 block diagram of the a-d0 converter ad0in0 ad0in1 ad0in2 ad0in3 ad0in4 ad0in5 ad0in6 ad0in7 selector interrupt request avss0 vref0 10-bit a-d successive approximation register (ad0sar) 10-bit a-d0 data register 0 10-bit a-d0 data register 1 single mode register a-d comparate data register a-d control circuit ? mode selection ? channel selection ? conversion time selection ? flag control ? interrupt control 10-bit d-a converter comparator ad0in8 ad0in9 ad0n10 ad0in11 ad0in12 ad0in13 ad0in14 ad0in15 ad0cmp ad0dt0 ad0dt1 ad0dt2 ad0dt3 ad0dt4 ad0dt5 ad0dt6 ad0dt7 ad0dt8 ad0dt9 ad0dt10 ad0dt11 ad0dt12 ad0dt13 ad0dt14 ad0dt15 dma transfer request successive approximation -type a-d converter unit internal data bus scan mode register p67/adtrg ad0scm0,1 ad0sim0,1 avcc0 output event bus 3 (multijunction timer) 10-bit readout 8-bit readout shifter 10-bit a-d0 data register 2 10-bit a-d0 data register 3 10-bit a-d0 data register 4 10-bit a-d0 data register 5 10-bit a-d0 data register 6 10-bit a-d0 data register 7 10-bit a-d0 data register 8 10-bit a-d0 data register 9 10-bit a-d0 data register 10 10-bit a-d0 data register 11 10-bit a-d0 data register 12 10-bit a-d0 data register 13 10-bit a-d0 data register 14 10-bit a-d0 data register 15
mitsubishi microcomputers 38 2001-5-14 rev.1.0 single-chip 32-bit cmos microcomputer 32170 group, 32174 group figure 26 block diagram of the a-d1 converter ad1in0 ad1in1 ad1in2 ad1in3 ad1in4 ad1in5 ad1in6 ad1in7 selector interrupt request avss1 vref1 10-bit a-d successive approximation register (ad1sar) 10-bit a-d1 data register 0 10-bit a-d1 data register 1 single mode register a-d comparate data register a-d control circuit ? mode selection ? channel selection ? conversion time selection ? flag control ? interrupt control 10-bit d-a converter comparator ad1in8 ad1in9 ad1n10 ad1in11 ad1in12 ad1in13 ad1in14 ad1in15 ad1cmp ad1dt0 ad1dt1 ad1dt2 ad1dt3 ad1dt4 ad1dt5 ad1dt6 ad1dt7 ad1dt8 ad1dt9 ad1dt10 ad1dt11 ad1dt12 ad1dt13 ad1dt14 ad1dt15 successive approximation -type a-d converter unit internal data bus scan mode register p67/adtrg ad1scm0,1 ad1sim0,1 avcc1 tid1 underflow /overflow 10-bit readout 8-bit readout shifter 10-bit a-d1 data register 2 10-bit a-d1 data register 3 10-bit a-d1 data register 4 10-bit a-d1 data register 5 10-bit a-d1 data register 6 10-bit a-d1 data register 7 10-bit a-d1 data register 8 10-bit a-d1 data register 9 10-bit a-d1 data register 10 10-bit a-d1 data register 11 10-bit a-d1 data register 12 10-bit a-d1 data register 13 10-bit a-d1 data register 14 10-bit a-d1 data register 15 note: the a-d converter does not have dma transfer request generation function.
mitsubishi microcomputers 39 single-chip 32-bit cmos microcomputer 2001-5-14 rev.1.0 32170 group, 32174 group 6-channel high-speed serial i/os the microcomputer contains six channels of serial i/os con- sisting of four channels that can be set for csio mode (clock-synchronized serial i/o) or uart mode (asynchro- nous serial i/o) and two other channels that can only be set for uart mode. the sio has the function to generate a dma transfer re- quest when data reception is completed or the transmit reg- ister becomes empty, and is capable of high-speed serial communication without causing any additional cpu load. table 20 outline of serial i/o item content number of channels csio/uart: 4 channels (sio0,sio1,sio4,sio5) uart only : 2 channels (sio2,sio3) clock during csio mode : internal clock / external clock, selectable (note1) during uart mode : internal clock only transfer mode transmit half-duplex, receive half-duplex, transmit/receive full-duplex brg count sourcef (bclk), f(bclk)/8, f(bclk)/32, f(bclk)/256 (when internal clock is selected) (note2) data format csio mode : data length = fixed to 8 bits order of transfer = fixed to lsb first uartmode : start bit = 1 bit character length = 7, 8, or 9 bits parity bit = added or not added (when added, selectable between odd and even parity) stop bit = 1 or 2 bits order of transfer = fixed to lsb first baud rate csio mode : 152 bits per second to 2 mbits per second (when operating with f(bclk) = 20 mhz) uartmode : 19 bits per second to 156 kbits per second (when operating with f(bclk) = 20 mhz) error detection csio mode : overrun error only uartmode : overrun, parity, and framing errors (the error-sum bit indicates which error has occurred) fixed cycle clock when sio0, sio1, sio4, or sio5 is in uart mode, this function outputs a 1/2 brg clock from the sclk pin. output function note 1: during csio mode, the maximum input frequency of an external clock is f(bclk) divided by 16. note 2: when f(bclk) is selected for the brg count source, the brg set value is subject to limitations.
mitsubishi microcomputers 40 2001-5-14 rev.1.0 single-chip 32-bit cmos microcomputer 32170 group, 32174 group figure 27 block diagram of serial i/o sclki0/ sclko0 bclk, bclk/8, bclk/32, bclk/256 baud rate generator (brg) bclk (set value + 1) 1 internal data bus csio mode when internal clock selected csio mode uart mode when internal clock selected 1/16 1/2 clock divider rxd0 txd0 receive interrupt transmit/ receive control circuit sio0 transmit buffer register sio0 transmit shift register receive dma transfer request transmit interrupt transmit dma transfer request to dmac3 sio0 receive shift register sio0 receive buffer register when extended clock selected when uart mode selected note 2: sio2 and sio3 do not have the sclki/sclko function. note 1: when bclk is selected, the brg set value is subject to limitations. sclki1/ sclko1 to dmac6 to interrupt controller sio0 sio1 sio2 sio3 rxd1 txd1 transmit/ receive control circuit sio1 transmit shift register sio1 receive shift register to dmac7 rxd2 txd2 transmit/ receive control circuit sio2 transmit shift register sio2 receive shift register to dmac9 rxd3 txd3 transmit/ receive control circuit sio3 transmit shift register sio3 receive shift register receive interrupt receive dma transfer request transmit interrupt transmit dma transfer request receive interrupt receive dma transfer request transmit interrupt transmit dma transfer request receive interrupt receive dma transfer request transmit interrupt transmit dma transfer request to interrupt controller to dmac8 to dmac5 to dmac3 to dmac4 sio4 rxd4 txd4 transmit/ receive control circuit sio4 transmit shift register sio4 receive shift register receive interrupt transmit interrupt sio5 rxd5 txd5 transmit/ receive control circuit sio5 transmit shift register sio5 receive shift register receive interrupt transmit interrupt sclki4 / sclko4 sclki5 / sclko5 to interrupt controller to interrupt controller
mitsubishi microcomputers 41 single-chip 32-bit cmos microcomputer 2001-5-14 rev.1.0 32170 group, 32174 group can module the m32170 and m32174 group contains two full can modules compliant with can specification v2.0b (can0 and can1), each of which has 16-channel message slots and three mask registers. figure 28 block diagram of the can module ctx crx can0 protocol controller 2.0b active can0 message slot 0-15 control register can0 global mask register can0 local mask register a can0 local mask register b can0 extended register message memory acceptance filtering 16-bit timer can0 time stamp register can0 configuration register can0 slot status register can0 slot interrupt control register can0 rec register can0 tec register can0 error interrupt control register interrupt control circuit can0 transmit/receive & error interrupt data bus (1) message id (2) data length code (3) message data (4) time stamp can0 status register can0 control register
mitsubishi microcomputers 42 2001-5-14 rev.1.0 single-chip 32-bit cmos microcomputer 32170 group, 32174 group 8-level interrupt controller the interrupt controller controls interrupt requests from each internal peripheral i/o (31 sources) by using eight pri- ority levels assigned to each interrupt source, including in- terrupts disabled. in addition to these interrupts, it handles system break interrupt (sbi), reserved instruction excep- tion (rie), and address exception (ae) as nonmaskable in- terrupts. wait controller the wait controller supports access to external devices. for access to an external extended area of up to 1 mbytes (during external extended or processor mode), the wait controller controls bus cycle extension by inserting one to ____ four wait cycles or using external wait signal input. real-time debugger (rtd) rtdclk rtdrxd rtdtxd rtdac k command address data internal ram m32r cpu 32170, 32174 group data data data bus(cpu ) data bus(rtd) r/w without cpu intervention virtual-dpram structure figure 29 conceptual diagram of the realtime debugger (rtd) realtime debugger (rtd) the realtime debugger (rtd) provides a function for ac- cessing directly from the outside to the internal ram. it uses a dedicated clock-synchronized serial i/o to communicate with the outside. use of the rtd communicating via dedicated serial lines al- lows the internal ram to be read out and rewritten without having to halt the cpu.
mitsubishi microcomputers 43 single-chip 32-bit cmos microcomputer 2001-5-14 rev.1.0 32170 group, 32174 group cpu instruction set the m32r employs a risc architecture, supporting a total of 83 discrete instructions. (1) load/store instructions perform data transfer between memory and registers. ld load ldb load byte ldub load unsigned byte ldh load halfword lduh load unsigned halfword lock load locked st store stb store byte sth store halfword unlock store unlocked (2) transfer instructions perform register to register transfer or register to immediate transfer . ld24 load 24-bit immediate ldi load immediate mv move register mvfc move from control register mvtc move to control register seth set high-order 16-bit (3) branch instructions used to change the program flow. bc branch on c-bit beq branch on equal beqz branch on equal zero bgez branch on greater than or equal zero bgtz branch on greater than zero bl branch and link blez branch on less than or equal zero bltz branch on less than zero bnc branch on not c-bit bne branch on not equal bnez branch on not equal zero bra branch jl jump and link jmp jump nop no operation (4) arithmetic/logic instructions perform comparison, arithmetic/logic operation, multiplica- tion/division, or shift between registers. ? comparison cmp compare cmpi compare immediate cmpu compare unsigned cmpui compare unsigned immediate ? logical operation and and and3 and 3-operand not logical not or or or3 or 3-operand xor exclusive or xor3 exclusive or 3-operand ? arithmetic operation add add add3 add 3-operand addi add immediate addv add (with overflow checking) addv3 add 3-operand addx add with carry neg negate sub subtract subv subtract (with overflow checking) subx subtract with borrow ? multiplication/division div divide divu divide unsigned mul multiply rem remainder remu remainder unsigned ? shift sll shift left logical sll3 shift left logical 3-operand slli shift left logical immediate sra shift right arithmetic sra3 shift right arithmetic 3-operand srai shift right arithmetic immediate srl shift right logical srl3 shift right logical 3-operand srli shift right logical immediate (5) instructions for the dsp function perform 32 bit 16 bit or 16 bit 16 bit multiplication or sum- of-products calculation. these instructions also perform rounding of the accumulator data or transfer between accu- mulator and general-purpose register. machi multiply-accumulate high-order halfwords maclo multiply-accumulate low-order halfwords macwhi multiply-accumulate word and high-order halfword macwlo multiply-accumulate word and low-order halfword mulhi multiply high-order halfwords mullo multiply low-order halfwords mulwhi multiply word and high-order halfword mulwlo multiply word and low-order halfword mvfachi move from accumulator high-order word mvfaclo move from accumulator low-order word mvfacmi move from accumulator middle-order word mvtachi move to accumulator high-order word mvtaclo move to accumulator low-order word rac round accumulator rach round accumulator halfword (6) eit related instructions start trap or return from eit processing. rte return from eit trap trap
mitsubishi microcomputers 44 2001-5-14 rev.1.0 single-chip 32-bit cmos microcomputer 32170 group, 32174 group figure 30 instructions for the dsp function rsrc1 0151631 hl 0151631 h l maclo instruction machi instruction rsrc2 acc 63 + 63 acc rsrc1 031 32 bit 0151631 h l macwlo instruction macwhi instruction rsrc2 acc 63 63 acc rsrc1 0151631 h acc 63 l 0151631 h l mullo instruction mulhi instruction rsrc 2 rsrc1 031 acc 63 0151631 hl mulwlo instruction mulwhi instruction rsrc2 32 bit 63 ac c rac instruction 63 ac c rach instruction < ropund off instruction > sign 0 data sign 0 data 63 63 rdest 1 63 15 16 31 47 48 mvfachi instruction ac c mvfaclo instruction mvfacmi instruction rsrc 031 63 31 32 ac c mvtaclo instruction mvtachi instruction < multiply instruction > < multiply-accumulate instruction > < accumulator - register transfer instruction > + + + 0 0 0 0 0 0 0 32 0 0 0 0 0 0
mitsubishi microcomputers 45 single-chip 32-bit cmos microcomputer 2001-5-14 rev.1.0 32170 group, 32174 group package dimensions diagram qfp240-p-3232-0.50 weight(g) C jedec code eiaj package code lead material cu alloy 240p6y-a plastic 240pin 32 ? 32mm body qfp C 0.35 C CC 0.45 C C CC C C C C C symbol min nommax a a 2 b c d e h e l l 1 y b 2 dimension in millimeters h d a 1 0.225 C C i 2 1.2 C C m d 32.6 C C m e 32.6 10 0 0.1 1.3 0.7 0.5 0.3 34.8 34.6 34.4 34.8 34.6 34.4 0.5 32.1 32.0 31.9 32.1 32.0 31.9 0.2 0.15 0.13 0.3 0.2 0.15 3.6 0.25 4.1 e e e e c h e 1 60 61 h d d m d m e a f b a 1 a 2 l 1 l y b 2 i 2 recommended mount pad detail f 240 120 121 180 181
mitsubishi microcomputers 46 2001-5-14 rev.1.0 single-chip 32-bit cmos microcomputer 32170 group, 32174 group 1234567891011121314151617181920 weight(g) C C jedec code eiaj package code 255f7f 255pin 17 ? 17mm body fbga 0.8 ? 19=15.2 a 0.8typ 17typ 0.8 ? 19=15.2 0.8typ b 1.2max c 0.1 c 0.35 0.05 (16.6) 17typ (16.6) 0.20 c b 0.2 ? 4 255- 0.45 0.05 0.08 c m a b under development 0.20 ca y w v u t r p n m l k j h g f e d c b a note: 255fbga is currently under development.
mitsubishi microcomputers 47 single-chip 32-bit cmos microcomputer 2001-5-14 rev.1.0 32170 group, 32174 group memo
single-chip 32-bit cmos microcomputer mitsubishi microcomputers 2001-5-14 rev.1.0 32170group, 32174group head office: 2-2-3, marunouchi, chiyoda-ku, tokyo 100-8310, japan ? 2001 mitsubishi electric corp. new publication, effective may 2001. specifications subject to change without notice. keep safety first in your circuit designs! ? mitsubishi electric corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. trouble with semiconductors may lead to personal injury, fire or property damage. remember to give due consideration to safety when making your circuit designs, with a ppropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap. notes regarding these materials ? these materials are intended as a reference to assist our customers in the selection of the mitsubishi semiconductor product b est suited to the customers application; they do not convey any license under any intellectual property rights, or any other rights, belonging to mitsubishi electric corporation or a third party. ? mitsubishi electric corporation assumes no responsibility for any damage, or infringement of any third-partys rights, origina ting in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. ? all information contained in these materials, including product data, diagrams, charts, programs and algorithms represents inf ormation on products at the time of publication of these materials, and are subject to change by mitsubishi electric corporation without notice due to product improvements or other reasons. it is therefore recommended that customers co ntact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor for the latest product information before purchasing a product listed herein. the information described here may contain technical inaccuracies or typographical errors. mitsubishi electric corporation assu mes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. please also pay attention to information published by mitsubishi electric corporation by various means, including the mitsubish i semiconductor home page (http://www.mitsubishichips.com). ? when using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. mitsubishi electric corporation assumes no responsibility for any damage, li ability or other loss resulting from the information contained herein. ? mitsubishi electric corporation semiconductors are not designed or manufactured for use in a device or system that is used und er circumstances in which human life is potentially at stake. please contact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor when considering the use of a product contained herei n for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. ? the prior written approval of mitsubishi electric corporation is necessary to reprint or reproduce in whole or in part these m aterials. ? if these products or technologies are subject to the japanese export control restrictions, they must be exported under a licen se from the japanese government and cannot be imported into a country other than the approved destination. any diversion or reexport contrary to the export control laws and regulations of japan and/or the country of destination is pro hibited. ? please contact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor for further detai ls on these materials or the products contained therein.
rev. revision description rev. no. page point date 1.0 first edition 010514 revision description list 32170 group, 32174 group data sheet (1/1)

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